By Michiel Steyaert, Arthur H.M. van Roermund, Herman Casier
Analog Circuit Design includes the contribution of 18 tutorials of the 17th workshop on Advances in Analog Circuit layout. each one half discusses a particular to-date subject on new and worthy layout principles within the quarter of analog circuit layout. each one half is gifted by means of six specialists in that box and cutting-edge info is shared and overviewed. This booklet is quantity 17 during this winning sequence of Analog Circuit Design.
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- Analog Circuit Design - High-Speed Clock And Data Recovery, High-Performance Amplifiers, Power Management
Additional info for Analog circuit design : high-speed clock and data recovery, high-performance amplifiers, power management
R. Walker, C. -S. 488 Gb/s Si-Bipolar Clock and Data Recovery IC with Robust Loss of Signal Detection”, Proceedings of the ISSCC, IEEE, February 1997, pp. 246–247. 3. J. 25-Gb/s Transceiver in 90-nm CMOS”, IEEE JSSC, Vol. 42, No. 12, December 2007, pp. 2745–2757. 4. T. 13 m CMOS”, of the 30th European Solid-State Circuits Conference, September 2004, pp. 487–490. 5. G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased techniques”, IEEE JSSC, Vol. 31, No. 11, November 1996, pp.
25 on average) is converted into +/− 1 by the phase detector. Transient domain simulations show that a low Integral Tracking (It) causes degradation in the high frequency jitter tolerance, thus requiring higher values of Ki. On the other hand, increasing Ki reduces the phase margin in the linear loop model, causing the negative peaking in the jitter tolerance. To improve the phase margin, Kp can be increased, but the overall latency of the digital loop again corrupts the jitter tolerance at high frequency, thus representing the main limitation to the overall CDR performances.
Unfortunately, the bang-bang detector leads to highly nonlinear behavior for the CDR since it can distinguish only the sign of the phase error, and not its magnitude. Since a consistent jitter transfer function implies linear dynamics, the bang-bang phase detector will not be suitable for high performance CDR applications such as SONET. One possible way of linearizing the bang-bang detector is to add extra levels to it as shown in Fig. 5. In this case, the magnitude of the phase error can be sensed in addition to its sign, though only in discrete intervals which are set by the delay of the buffers shown in the figure.