Download Computing with Memory for Energy-Efficient Robust Systems by Somnath Paul PDF

By Somnath Paul

This publication analyzes power and reliability as significant demanding situations confronted through designers of computing frameworks within the nanometer expertise regime. The authors describe the present recommendations to handle those demanding situations after which exhibit a brand new reconfigurable computing platform, which leverages high-density nanoscale reminiscence for either information garage and computation to maximise the energy-efficiency and reliability. The strength and reliability advantages of this new paradigm are illustrated and the layout demanding situations are mentioned. numerous and software program features of this interesting computing paradigm are defined, rather with recognize to hardware-software co-designed frameworks, the place the unit may be reconfigured to imitate assorted program habit. eventually, the energy-efficiency of the paradigm defined is in comparison with different, famous reconfigurable computing platforms.

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Online], “Mosaic Developing power-efficient coarse-grained reconfigurable architectures and tools”. edu/research/projects/lis/www/mosaic/ 10. H. Singh, M. Lee, G. J. Kurdahi, N. M. Chaves Filho, “MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications”. IEEE Trans. Comput. 49(5), 465–481 (2000) 11. C. Goldstein, H. Schmit, M. Moe, M. Budiu, S. R. Taylor, R. Laufer, “PipeRench: A Coprocessor for Streaming Multimedia Acceleration”, in Intl. Symp. on Computer Architecture, 1999 12.

Paul, F. Cai, X. Zhang, S. Bhunia, “Reliability-driven ECC allocation for multiple bit error resilience in processor cache”. IEEE Trans. Comput. 60(1), 20–34 (2011) 41. S. Srinivasan, A. Gayasen, N. Vijaykrishnan, M. Kandemir, Y. J. Irwin, “Improving Soft-Error Tolerance of FPGA Configuration Bits”, in ICCAD, 2004 42. Y. Lin, L. He, M. Hutton, “Stochastic physical synthesis considering prerouting interconnect uncertainty and process variation for FPGAs”. IEEE Trans. Very Large Scale Integrat. Syst.

As the technology is scaled further, we believe LUTs with larger input size would be more area efficient. In addition to LUT clusters, modern FPGAs have become heterogenous by incorporating custom adders, multipliers and memory elements. With only LUT based function evaluation, the performance gap between FPGAs and ASICs were estimated to be 40×. This gap however reduces to 21× by incorporating the hard adder and multiplier elements [27]. Finally, to improve the performance of interconnects, researchers have looked into pipelining of FPGA interconnects [48].

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